Field of the Invention
This invention relates generally to the field of computer processors. More particularly, the invention relates to an apparatus and method for recovering from a bad store-to-load forwarding in an out-of-order processor.
Description of the Related Art
In pipelined execution systems, instruction are fetched, decoded, and executed speculatively. Techniques such as reordering of memory operations (e.g., hoisting of loads over older stores), removal of duplicate load instructions, and use of store-to-load forwarding have proven to be effective mechanisms for improving the performance of Out-of-Order (OoO) microprocessors. Associated with speculative execution of instructions are rules to be observed and means to detect when these rules are violated so that appropriative corrective measures can be taken. Additionally, it would be beneficial if the outcome of certain instructions (e.g., bad loads) can be predicted before they are executed.
For example, in the context of store-to-load forwarding, current implementations are typically restricted to only fully overlapped store/load accesses where an older store buffer entry completely covers the region of memory being read by a younger load instruction. In cases where store/load accesses overlap only partially or are of different sizes, such that the younger load instruction attempts to access a region of memory not covered by the older store buffer entry, the store-to-load forwarding mechanism would fail. This often leads to the processor stalling until the offending conditions are cleared which, consequently, causes degradation in performance. Moreover, as no history or memory is kept for bad store-to-load forwarding occurrences, a bad load instruction is detected only when a lookup in the store-buffer is performed at runtime. This often leads to unnecessary/duplicative lookups and imposes additional power and performance cost that could have been avoided.